佐须之男的博客

技术需要沉淀,成长需要痛苦,成功需要坚持,敬仰需要奉献

Broadcom 博通 sdram相关参数说明


This pages focus on memory controller configuration values, stored in the nvram and used for BCM3302 memory controller configuration found in the BCM4712, BCM53xx series of SoC and BCM5836 CPU

There are several references, which was used to make this summary page, including GPL source code tarballs, distributed by Linksys and ASUS and CFE distributed by Broadcom.

Memory configuration is perfromed by code, assembled from shared/sbsdram.S file. Depending on version it's either uses embedded nvram header values (found in PMON/CFE loader at offset 0x100 or 0x400) or values, from current nvram. These values are generated from sdram_* values either during bootloader flashing or via nvram update using nvram commit command.

The exact sdram configuration variables are: sdram_init, sdram_config, sdram_refresh and sdram_ncdl. They are used as following:

  • sdram_init determines the memory controller operation mode, i.e. DDR/SDR cycles, 16/32 bit memory interface, number of bits in CAS signal, etc.:

    FieldNameDescription
    0MemTypeMemory type in use.
    0: SDR SDRAM
    1: DDR SDRAM
    116BitMemMemory interface.
    0: 32-bit interface
    1: 16-bit interface
    4:2ColWidthColumn width in use.
    000: 8-bit column
    010: 9-bit column
    100: 10-bit column
    13ClockClock source?
    0: External clock
    1: Internal clock
  • sdram_config is used to initialize the mode register (during MRS cycle) of the SDRAM, it contains things defined by JEDEC: burst type, burst length, CAS latency;

    FieldNameDescription
    0:2BurstLengthBurst Length value.
    000: 1
    001: 2
    010: 4
    011: 8
    111: full page
    3BurstTypeBurst Type value.
    0: Sequential
    1: Interleave
    6:4CASLatencyCAS Latency.
    001: 1
    010: 2
    011: 3
    101: 1.5
    110: 2.5
    111: 3.5
  • sdram_refresh seems to be leaved for compatibility, and not used anymore;

  • sdram_ncdl contains various memory controller timing information, this could be either 0, which indicates to perform auto-tuning during memory initialzation (it will be updated to real value once initialization completed by CFE) or predefined value.

Sample memory configurations which could be found in the sources provided by Broadcom:


SizeTypeOrganizationsdram_initbitsRASCASTechnology
8MBSDR4 Meg x 160x0002000 1 0A0-A11A0-A764Mbit
16MBSDR4 Meg x 16 x 20x0000000 0 0A0-A11A0-A764Mbit
16MBSDR8 Meg x 160x000a010 1 0A0-A11A0-A8128Mbit
32MBDDR16 Meg x 160x000b010 1 1A0-A12A0-A8256Mbit
32MBSDR16 Meg x 160x000a010 1 0A0-A12A0-A8256Mbit
32MBSDR8 Meg x 16 x 20x0008010 0 0A0-A11A0-A8128Mbit
64MBDDR16 Meg x 16 x 20x0009010 0 1A0-A12A0-A8256Mbit
64MBSDR16 Meg x 16 x 20x0008010 0 0A0-A12A0-A8256Mbit
128MBDDR32 Meg x 16 x 20x0011100 0 1A0-A12A0-A9512Mbit
128MBSDR32 Meg x 16 x 20x0010100 0 0A0-A12A0-A9512Mbit
256MBDDR64 Meg x 16 x 20x0011100 0 1A0-A13A0-A91Gbit





Powered By Z-BlogPHP 1.5 Zero

© 2016 佐须之男版权所有 | 联系方式 forgotfun@qq.com | 业务合作 181-1435-4589 (陆工)